1. Field of Invention
The invention relates to a method of preparing a sidewall spacer for a transistor gate on a substrate.
2. Description of Related Art
In semiconductor manufacturing and during the fabrication of a transistor gate, a spacer material is conformally applied to the transistor gate, and then partially removed to form a sidewall spacer on a sidewall of the transistor gate. During the partial removal of the spacer material from the transistor gate top and the substrate, the success of a spacer etch process is determined by measuring, among other things, the following performance metrics: (a) the size of the sidewall spacer footing, (b) the depth of the substrate recess, (c) the amount of sidewall spacer critical dimension (CD) slimming, and (d) the depth of the spacer top recess. Conventional spacer etch processes produce unacceptable results in at least one of these performance metrics.
In addition, as the device nodes are shrinking, parasitic capacitances between the gate and the episilicon facets and between the gates and the contacts are causing device degradations and can no longer be ignored. To minimize these parasitic capacitances, one can lower the K-value of the gate spacer. Conventional spacers materials in use are typically atomic layer deposited silicon nitride and have a K-value around 7 to 7.5. New spacer material candidates have emerged to remedy this issue such as SiBCN or SiOCN. These films although presenting lower K advantages bring integration concerns as their dry etch and wet etch properties may differ from that of conventional spacer material. There is a need to identify the key spacer etch variables and determine the critical ranges for these key spacer etch variables. Furthermore, there is a need for methods and systems that can address the need to reduce the K-value of spacers and also resolve the integration issues in etch properties of the resulting spacers when new low-k materials are considered. The benefits and impact of the steps in the integration flow must be evaluated in order to assess the places where spacer processing can be implemented without adversely affecting the other structures in the substrate.